The Mark 2 Z80 project featured a pair of memory slots each capable of taking up to 32K of RAM. This meant that a full 64K of RAM could be used because the ROM image is copied from the PIC's memory at boot time. However that didn't seem like much to me so a banking system and MMU were in order. (Also I found I couldn't get the 32K RAMTRON FM1808 chips in DIP any more!)
The new system is designed around 512K SRAM chips, up to 8 of them, although I've only wired up two sockets for 1MB of RAM for now. If you know your base 2 maths you should realise that I need a 22 bit address bus for the 4MB address space. This initially seems like an odd size but the design is based on the internals of the Amstrad NC100, a portable Z80 machine from the early '90s. The top 8 bits of the 22 are provided by one of four latches. Which of these latches provides the last 8 bits is decided by the Z80 address lines A14 and A15.
This means the physical memory space of the Z80 is made up by four 16KB pages, each of which can contain any 16KB from the 4MB address space. This is a somewhat confusing arrangement to think about at first but can be immensely powerful. In the case of a CP/M 3.0 system the top 16KB can be left in place and the remaining 48KB switched, but because any block of memory can be placed in any of the four physical address bus 16KB blocks then no memory is wasted with a 48K banking scheme. In a more flexible purpose written system the fact that any memory block can be resident in any of the four areas at any time could allow block to block copying from any source and destination block. Boot strap code can be placed in the first block and a jump to the next instruction but in the last 16KB block can be carried out to allow bank switching of the running code without risk to system stability.
To ensure that the system can boot with this system an overall config register is included, I've used a 74HCT273 8 bit latch with reset to store the config register so that its state is known at boot, however I only use one bit of the register at the moment so a simple D type flip flop would suffice. The first bit in this register is inverted and then used as the enable line to the 74HCT139 that selects which of the four bank select registers drives the upper 8 bits. These are normal 74HCT574 latches with tri-state outputs, the resetable types don't have the tri-state option so wouldn't be any good in this situation where any of the four needs to be able to drive the same bus. Since the enable is held high until the config register is written to, none of the four bank select registers are ever allowed to drive the 8 high address bits, these are pulled low by a bank of resistors, so at boot up each of the four 16KB blocks accesses the first 16KB of physical RAM. The current BIOS/bootloader code in the PIC understands this and sets up the memory to be a single linear 64KB of RAM at the bottom of the available memory before loading any other code, so as far as non-bank aware code is concerned the system has a full compliment of 64KB of RAM.
Check out the new memory board's schematic for details on how I wired it all up, the new BIOS with an updated memory test routine is in the github repository.
|z80_mark2-Memory2.pdf||April 23, 2014, 9:06 p.m.||176.1 KB|