Z80 Project

I recently received an enquiry about how the I/O throttling on the PIC worked to ensure that the PSP was shifting valid data out to the Z80. I had a look back at my code and figured out how I'd done it. However I realised in that conversation that the schematics for the project were vastly out of date and it seemed that I hadn't been keeping as up to date as I thought I was with my local copies. I've spent several evenings in the last week and more or less re-drawn all the schematics from scratch, referencing the old snippets and the code and occasionally resorting to the continuity tester!

The schematics are in a number of fairly self contained PDFs here, I'll push the KiCAD source to git hub in the new year after I've finished my Christmas trips. Each unit of the system is mainly only connected by the Z80 busses (data, control and address) although the interrupt controller and the I/O decode have a lot of ancillary signals in them. Hopefully this is all fairly clear, it includes the previously un-published graphics driver and the keyboard reading PIC. There are also some modifications to the master PIC that allow it to re-use some of the address lines when it isn't being a master.

Currently the written documentation doesn't match up very accurately, several of the port pin definitions aren't right and some things like the RTC seem entirely missing from the I/O port listings. Hopefully this content should be interesting/useful to someone though. It should make a much sounder basis if I ever get around to working on a real OS or moving on to the Mark 3 project I've been thinking about for a long time.